1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly, to a vertical surround gate metal-oxide semiconductor field-effect transistor (hereinafter referred to as "MOSFET"). The present invention further relates to a dynamic random access memory, an inverter circuit, and a static random access memory using such a vertical surround gate MOSFET. The present invention also relates to a method of manufacturing such a semiconductor device.
2. Description of the Background Art
FIG. 101 is a schematic diagram of a conventional planar type MOSFET. Referring to FIG. 101, a gate electrode 3 is provided on a P-type silicon substrate 1 with a gate insulating film 4 interposed therebetween. N-type source/drain regions 6a, 6b are provided on both sides of gate electrode 3 in the main surface of silicon substrate 1.
Operation of the conventional Mosfet will now be described. When a positive potential is applied to gate electrode 3, the following reaction occurs in the main surface of silicon substrate 1 EQU B.fwdarw.B.sup.- +h.sup.+
where B is boron, B.sup.- is a boron anion, and h.sup.+ is a hole.
More specifically, when a positive potential is applied to gate electrode 3, boron is separated into boron anions and holes. Boron anions are attracted to gate electrode 3. On the other hand, holes repulse gate electrode 3 to escape in silicon substrate 1, which in turn generates a depletion layer 17 in the main surface of a channel region of silicon substrate 1. Depletion layer 17 is a region where neither electrons nor holes exist, that is, where no carriers serving to make a current flow exist.
As a positive potential applied to gate electrode 3 is increased, depletion layer 17 is enlarged and its width Wd is increased. However, increase of the width Wd of depletion layer 17 is limited. The width of depletion layer 17 is determined by an impurity concentration. The larger the impurity concentration, the narrower the width Wd of the depletion layer. The smaller the impurity concentration, the wider the width Wd. The maximum value of the width Wd of depletion layer 17 is called maximum depletion layer width.
When the width Wd of depletion layer 17 reaches the maximum depletion layer width, an inversion layer 18 is formed on the surface of the channel region, rendering source 6a/drain 6b conductive.
When the integration density of a semiconductor device is increased, an area occupied by the MOSFET needs to be small.
FIG. 102 is a perspective view extracting and illustrating main portions of the conventional vertical type surround gate MOSFET improved so that an area occupied by the MOSFET may be made small.
Referring to FIG. 102, gate electrode 3 surrounds a plug-shaped silicon 5 with gate insulating film 4 interposed therebetween. Source region 6a is provided at an upper end of plug-shaped silicon 5, and drain region 6b is provided at a lower end thereof. Drain region 6b is formed in the main surface of the silicon substrate.
Aluminum interconnections 10a, 10b, and 10c are connected to source region 6a, gate electrode 3, and drain region 6b, respectively.
When a positive potential is applied to gate electrode 3, an inversion layer is generated on the sidewall surface of the plug-shaped silicon, causing a current to flow from source region 6a to drain region 6b. In other words, the current flows in the direction perpendicular to the silicon substrate.
Comparison is now made between an area occupied by the planar type MOSFET and an area occupied by the vertical type surround gate MOSFET.
Let L be a gate length of the planar type MOSFET, and W be a channel width of the planar type MOSFET, referring to FIG. 101, an occupied area Splanar of the channel region is EQU Splanar=L.multidot.W
On the other hand, in the case of the vertical type surround gate MOSFET, referring to FIG. 103 (which is a simplification of FIG. 102), when the radius of the channel region is R, the channel width W is 2.pi.R. An occupied area of the channel region is EQU Svertical=.pi.R.sup.2 =W.sup.2 /4.pi.
Therefore, when transistors having the gate length L equal to the channel width W are formed of a planar type MOSFET and a vertical type surround gate MOSFET, respectively, the ratio of respective occupied areas is EQU Svertical/Splanar=1/4.pi.
More specifically, an occupied area of the vertical type surround gate MOSFET is 1/12 or less of that of the planar type MOSFET.
If occupied areas of both the vertical type surround gate MOSFET and the planar type MOSFET are made equal, it is possible to increase W in the vertical type surround gate MOSFET. This is a first advantage of the vertical type surround gate MOSFET.
Referring to FIGS. 102 and 103, in the vertical type surround gate MOSFET, it is possible to deplete the entire channel by decreasing the radius of channel plug 5. Therefore, the vertical type surround gate MOSFET has advantages the same as those of a conventional SOI (Silicon-On-Insulator) MOSFET. Detailed description thereof will be given hereinafter.
If the entire channel can be depleted, it is possible to suppress a subthreshold current (a leakage current in a weakly inverted state), which in turn improves a circuit characteristic.
A subthreshold coefficient S is expressed by the following expression: EQU S=ln10.multidot.kT/q.multidot.(1+Cd/Cox)
where k is a Boltzmann constant, T is an absolute temperature, q is an elementary electric charge, Cd is a depletion layer capacitance of the MOSFET, and Cox is a gate insulating film capacitance.
As is clear from the above equation, when Cd=0 holds, the subthreshold coefficient S takes the minimum value (ln10.multidot.kT/q=60 mV/dec).
FIG. 104 is a cross-sectional view of an SOIMOSFET. An SIO layer 15 is formed on a buried oxide film 16. Gate electrode 3 is formed on SOI layer 15 with gate insulating film 4 interposed therebetween. Source/drain regions 6a, 6b are formed on both sides of gate electrode 3 in the surface of SOI layer 15. In the figure, Wd is a depletion layer width, t.sub.SOI is the film thickness of SOI layer 15, and t.sub.BOX is the film thickness of buried oxide film 16.
When the entire SOI layer 15 is not depleted (that is, when Wd&lt;t.sub.SOI holds), the depletion layer capacitance Cd of the SOIMOSFET is, similar to the case of the MOSFET shown in FIG. 101, expressed by the following equation: EQU Cd=.epsilon..sub.si /Wd
On the other hand, when the film thickness of buried oxide film 16 is sufficiently larger than that of SOI layer 15 (t.sub.BOX &gt;&gt;t.sub.SOI), and the entire SOI layer 15 is depleted (when it is in a fully depleted state, Wd.gtoreq.t.sub.SOI), the depletion layer capacitance Cd is substantially 0. In the case of the SOIMOSFET, it is possible to make the depletion layer capacitance Cd zero by adjusting the film thickness of SOI layer 15, thereby suppressing a subthreshold current.
The above-described advantage of the SOIMOSFET can be implemented in the vertical type surround gate MOSFET. More specifically, when the fully depleted state is implemented in the vertical type surround gate MOSFET, the depletion layer capacitance Cd is 0 similar to the case of the SOIMOSFET. Since electric power lines extend in the radial direction, the phenomenon of which is unique to the surround type MOSFET, the depletion layer capacitance Cd is smaller than that of the MOSFET shown in FIG. 101 even in the state of incomplete depletion.
The following equation shows the relation between the radius R and the depletion layer capacitance Cd of the vertical type surround gate MOSFET, and FIG. 105 shows the equation in the form of graph. ##EQU1##
When R/Wd&lt;1 holds, complete depletion of the channel can be implemented. Therefore, the depletion layer capacitance Cd is 0. Even if R/Wd&gt;1 holds, the depletion layer capacitance Cd is smaller than that of a bulk MOSFET shown in FIG. 100.
As described above, in the vertical type surround gate MOSFET, it is possible to make the depletion layer capacitance Cd zero by adjusting the radius of channel plug 5, which in turn makes it possible to suppress the subthreshold current. As a result, the vertical type surround gate MOSFET has a second advantage of improving a circuit characteristic.
A third advantage of the vertical type surround gate MOSFET is that the entire channel plug can be made an inversion layer, thereby increasing a drain current.
As described above, the vertical type surround gate MOSFET has three advantages.
FIGS. 106 to 109 are partial cross-sectional views of a semiconductor device in respective steps of the manufacturing process of the conventional vertical type surround gate MOSFET.
Referring to FIG. 106, plug-shaped silicon 5 of the vertical type surround gate MOSFET is formed by anisotropically etching substrate 1. Plug-shaped silicon 5 is cylindrical when represented in a perspective view as shown in FIG. 111.
Referring to FIG. 107, gate insulating film 4 is deposited on substrate 1 so as to cover plug-shaped silicon 5. Then, impurity ions are implanted into the surface of substrate 1 through gate insulating film 4 to form source region 6a and drain region 6b.
Referring to FIG. 108, polysilicon 3 serving as a gate electrode is deposited on substrate 1.
Referring to FIGS. 108 and 109, polysilicon 3 is selectively etched to form gate electrode 3.
Referring to FIG. 110, an interlayer insulating film 2 is deposited on substrate 1 so as to cover gate electrode 3. A contact hole for exposing the surface of source region 6a, a contact hole for exposing a part of the surface of gate electrode 3, and a contact hole for exposing a part of the surface of drain region 6b are formed in interlayer insulating film 2. By connecting aluminum interconnections 10a, 10b, 10c to respective portions through these contact holes, the vertical type surround gate MOSFET shown in FIG. 102 is completed.
Although the conventional vertical type surround gate MOSFET had three advantages as described above, it also had the following problems.
Referring to FIG. 102, the diameter of plug-shaped silicon 5 must be made larger than a contact hole 8a so that aluminum interconnection 10a connected to drain region 6a and gate electrode 3 might not be short-circuited. Formation of large plug-shaped silicon 5 causes an area occupied by the device to increase. Formation of large plug-shaped silicon 5 also causes the channel plug not to be depleted completely, resulting in no inversion of the entire channel plug. Therefore, the conventional vertical type surround gate MOSFET was not able to fully enjoy the above-described three advantages.